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41D1C855D
863C@39 9C4>"24C 9C4>84<3696?S_^db_\\Ub gYdX CDQ^T@39Y^dUbVQSU Q^T ESXYce_bd
Copyright 1994-1999 Cologne Chip Designs GmbH All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by patent or other rights.
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Revision History
Date Feb. 1999 Jan. 1999 Sep. 1998 Aug. 1998 Aug. 1998 July 1998 July 1998 June 1998 May 1998 Remarks Changes made on: CLKDEL register bit description. New chip released: HFC-S PCI A is compliant to PCI Spec 2.2. The old chip HFC-S PCI is not recommended for new projects. Changes made on: Electrical characteristics, Part List: C3 and C4 must be 22pF. Changes made on: FIFO_EN register bit description. Changes made on: Part List: C3 and C4 must be 47pF, C5 and C6 have been removed. changes made on: PCI buffer signaling and power supply environment, PCI configuration registers, B_MODE register bit description changes made on: Block diagram, sample circuitry, Part List: Q2 and Q3 must be BC850C instead of BC848B schematic of PCI sample board corrected; digital part added changes made on: RESET characteristics, PCI modes supported, PCI buffer signaling environment, PCI configuration registers, timer, FIFO counters location in MW, automatically D-channel frame repetition, FIFO initialisation, TRxR register bit description, CTMT register bit description, CHIP_ID register bit description, FIFO_EN register bit description, TRM register bit description, electrical characteristics, S/T module part numbers and manufacturers, sample circuitry
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Contents
1 General description.................................................................................................................................. 6 1.1 Applications ............................................................................................................................................ 7 2 Pin description.......................................................................................................................................... 8 2.1 PCI bus interface..................................................................................................................................... 8 2.2 Auxiliary port........................................................................................................................................ 10 2.3 S/T interface transmit signals ............................................................................................................... 10 2.4 S/T interface receive signals ................................................................................................................. 10 2.5 Oscillator............................................................................................................................................... 11 2.6 GCI/IOM2 bus interface ....................................................................................................................... 11 2.7 GCI/IOM2 Timeslot enable signals ...................................................................................................... 11 2.8 EEPROM interface ............................................................................................................................... 11 2.9 Power supply......................................................................................................................................... 12 2.10 RESET characteristics ........................................................................................................................ 12 3 Functional description........................................................................................................................... 13 3.1 PCI-interface ......................................................................................................................................... 13 3.1.1 PCI access types used by HFC-S PCI............................................................................................ 13 3.1.2 PCI modes supported..................................................................................................................... 13 3.1.3 PCI buffer signaling and power supply environment .................................................................... 13 3.1.4 PCI configuration registers............................................................................................................ 14 3.2 Internal HFC-S PCI register description............................................................................................... 17 3.2.1 Registers of the S/T section........................................................................................................... 18 3.2.2 Registers of the GCI/IOM2 bus section ........................................................................................ 19 3.2.3 Interrupt and status registers.......................................................................................................... 20 3.3 Timer..................................................................................................................................................... 21 3.4 FIFOs .................................................................................................................................................... 22 3.4.1 FIFO counters location in Memory Window ................................................................................ 23 3.4.2 FIFO data location in Memory Window ....................................................................................... 24 3.4.3 FIFO channel operation ................................................................................................................. 25 3.4.3.1 Send channels (B1, B2 and D transmit) ................................................................................. 25 3.4.3.2 Automatically D-channel frame repetition............................................................................. 26 3.4.3.3 FIFO full condition in send channels ..................................................................................... 26 3.4.3.4 Receive Channels (B1, B2 and D receive)............................................................................. 26 3.4.3.5 FIFO full condition in receive channels................................................................................. 28 3.4.3.6 FIFO initialisation .................................................................................................................. 28 3.4.4 Transparent mode of HFC-S PCI .................................................................................................. 29 4 Register bit description ......................................................................................................................... 30 4.1 Register bit description of S/T section ................................................................................................. 30 4.2 Register bit description of GCI/IOM2 bus section ............................................................................... 33 4.3 Register bit description of CONNECT register.................................................................................... 36 4.4 Register bit description of auxiliary and cross data registers ............................................................... 37 5 Electrical characteristics ....................................................................................................................... 42 6 Timing characteristics ........................................................................................................................... 46 6.1 PCI bus timing ...................................................................................................................................... 46 6.2 GCI/IOM2 bus clock and data alignment for Mitel STTM bus.............................................................. 46 6.3 GCI/IOM2 timing.................................................................................................................................. 47 6.4 EEPROM access ................................................................................................................................... 48
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7 S/T interface circuitry ........................................................................................................................... 49 7.1 External receiver circuitry .................................................................................................................... 49 7.2 External transmitter circuitry................................................................................................................ 50 7.3 Oscillator circuitry ................................................................................................................................ 53 7.4 EEPROM circuitry................................................................................................................................ 53 7.5 PME pin circuitry.................................................................................................................................. 54 8 State matrices for NT and TE............................................................................................................... 55 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT ......................................... 55 8.2 Activation/deactivation layer 1 for finite state matrix for TE .............................................................. 56 9 Binary organisation of the frames........................................................................................................ 57 9.1 S/T frame structure ............................................................................................................................... 57 9.2 GCI frame structure .............................................................................................................................. 58 10 Clock synchronisation ......................................................................................................................... 59 10.1 Clock synchronisation in NT-mode .................................................................................................... 59 10.2 Clock synchronisation in TE-mode .................................................................................................... 60 11 HFC-S PCI package dimensions ........................................................................................................ 61 12 ISDN PCI card sample circuitry with HFC-S PCI........................................................................... 62
Figures
Figure 1: HFC-S PCI block diagram............................................................................................................. 7 Figure 2: Pin Connection .............................................................................................................................. 8 Figure 3: HFC-S PCI in I/O address mapped mode.................................................................................... 17 Figure 4: HFC-S PCI in memory address mapped mode............................................................................ 17 Figure 5: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 25 Figure 6: FIFO Data Organisation .............................................................................................................. 27 Figure 7: Function of the CONNECT register bits..................................................................................... 36 Figure 8: GCI/IOM2 bus clock and data alignment.................................................................................... 46 Figure 9: External receiver circuitry........................................................................................................... 49 Figure 10: External transmitter circuitry .................................................................................................... 50 Figure 11: Oscillator Circuitry.................................................................................................................... 53 Figure 12: EEPROM circuitry .................................................................................................................... 53 Figure 13: PME pin circuitry ...................................................................................................................... 54 Figure 14: Frame structure at reference point S and T ............................................................................... 57 Figure 15: Single channel GCI format........................................................................................................ 58 Figure 16: Clock synchronisation in NT-mode .......................................................................................... 59 Figure 17: Clock synchronisation in TE-mode........................................................................................... 60 Figure 18: HFC-S PCI package dimensions ............................................................................................... 61
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Tables
Table 1: PCI command types ...................................................................................................................... 13 Table 2: PCI configuration registers' initial values..................................................................................... 17 Table 3: S/T module part numbers and manufacturer ................................................................................ 52 Table 4: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 55 Table 5: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 56
Timing Diagrams
Timing diagram 3: GCI/IOM2 timing......................................................................................................... 47 Timing diagram 4: EEPROM access .......................................................................................................... 48
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Features

One chip ISDN-S-controller with B- and D-channel HDLC support Independent Read and Write HDLC-Channels for 2 ISDN B-channels and one ISDN D-channel B1- and B2-channel transparent mode independently selectable FIFO-Memory-Window: 4x 7.5 KByte (B-channel) and 2x 512 Byte (D-channel) max. 31 HDLC frames (B-channel) and 15 HDLC frames (D-channel) per channel and direction in FIFO 56 kbit/s restricted mode for U.S. ISDN lines selectable full I.430 ITU S/T ISDN support in TE and NT mode B1+B2 HDLC mode PCM30 interface configurable to interface MITEL STTM bus (MVIPTM), Siemens IOM2TM or GCITM for interface to U-chip or external codecs integrated PCI Spec. 2.1 bus interface for 3.3V and 5V bus signals direct access to PCM30 interface for tone synthetisation 3.3V and 5V supply voltage rectangular QFP 100 case
1
General description
The HFC-S PCI is an ISDN S/T HDLC basic rate controller for so called passive" ISDN PC cards with integrated S/T interface and PCM30 highway interface. It is the first all in one solution for a PCI ISDN PC-card world wide with power management and Windows 98 support. A 32Kbyte memory window of the PC is used for the deep FIFOs. Also an industrial standard serial interface for telecom peripheral ICs is implemented. Codecs are normally connected to this interface.
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1.1
Applications ISDN PCI PC card
Figure 1: HFC-S PCI block diagram
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2
Pin description
Figure 2: Pin Connection
2.1
PCI bus interface
For further information please refer to the PCI Local Bus Specification. Pin No. Pin Name Input Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function PCI address bus Address bit 0 Address bit 1 Address bit 2 Address bit 3 Address bit 4 Address bit 5 Address bit 6 Address bit 7 Address bit 8 Address bit 9 Address bit 10 Address bit 11 Address bit 12 Address bit 13 Address bit 14 Address bit 15
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47 46 45 44 43 42 41 40 37 36 35 34 33 32 31 30
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AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
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Pin No. 16 15 14 13 12 11 10 9 4 3 2 1 100 99 98 97 26 38 27 18 5 93 92 19 20 21 23 6 22 95 94 24 25 53 91
Pin Name AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PAR C/BE0 C/BE1 C/BE2 C/BE3 CLK RST# FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQ# GNT# PERR# SERR# PME INTA#
Input Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I I/O O I I/O O O O
Function Address bit 16 Address bit 17 Address bit 18 Address bit 19 Address bit 20 Address bit 21 Address bit 22 Address bit 23 Address bit 24 Address bit 25 Address bit 26 Address bit 27 Address bit 28 Address bit 29 Address bit 30 Address bit 31 Parity bit Bus command and byte enable 0 Bus command and byte enable 1 Bus command and byte enable 2 Bus command and byte enable 3 PCI clock Reset Cycle frame Initiator ready Target ready Stop Initialisation device select Device select Request Grant Parity error System error Power management event (high active) see also: Figure 13 on page 54 Interrupt A
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2.2
Auxiliary port Pin Name DAUX0 DAUX1 DAUX2 DAUX3 DAUX4 DAUX5 DAUX6 DAUX7 /AUX_WR /AUX_RD /ADR_WR Input Output I/O I/O I/O I/O I/O I/O I/O I/O O O I/O d) Function AUX data bit 0 AUX data bit 1 AUX data bit 2 AUX data bit 3 AUX data bit 4 AUX data bit 5 AUX data bit 6 AUX data bit 7 AUX write AUX read AUX address write
Pin No. 75 74 73 72 71 70 69 68 67 66 65
d)
internal pull down
2.3 88 87 86 85 84
S/T interface transmit signals TX2_HI /TX1_LO /TX_EN /TX2_LO TX1_HI O O O O O Transmit output 2 GND driver for transmitter 1 Transmit enable GND driver for transmitter 2 Transmit output 1
See also: 7.2 External transmitter circuitry.
2.4 82 81 80 79 78
S/T interface receive signals R2 LEV_R2 LEV_R1 R1 ADJ_LEV I I I I O Receive data 2 Level detect for R2 Level detect for R1 Receive data 1 Levelgenerator
See also: 7.1 External receiver circuitry.
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2.5
Oscillator Pin Name OSC_IN OSC_OUT Input Output I O Function Oscillator input or quarz connection 12.288 MHz Oscillator output or quarz connection
Pin No. 51 50
2.6 54
GCI/IOM2 bus interface C4IO I/O u) I/O u) 4.096 MHz clock GCI/IOM2 bus clock master: output GCI/IOM2 bus clock slave: input (reset default) Frame synchronisation, 8kHz pulse for GCI/IOM2 bus frame synchronisation GCI/IOM2 bus master: output GCI/IOM2 bus slave: input (reset default) GCI/IOM2 bus databus I Slotwise programmable as input or output GCI/IOM2 bus databus II Slotwise programmable as input or output
55
F0IO
56 57
STIO1 STIO2
I/O u) I/O u)
u)
internal pull up
2.7 GCI/IOM2 Timeslot enable signals (e. g. for PCM codecs) 58 59 F1_A F1_B O O enable signal for external CODEC A Programmable as positive (reset default) or negative pulse. enable signal for external CODEC B Programmable as positive (reset default) or negative pulse.
2.8
EEPROM interface
The external EEPROM is optional. EE_SCL/EN must be connected to GND if no external EEPROM is available. 63 62
u)
EE_SDA EE_SCL/EN
I/O u) I/O u)
Serial data of external EEPROM Clock of external EEPROM / EEPROM enable
internal pull up
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2.9
Power supply Pin Name VDD GND Function VDD (+3.3V or +5V) GND
Pin No. 7, 28, 48, 60, 76, 89 8, 17, 29, 39, 49, 52, 61, 64, 77, 83, 90, 96
* important!
All power supply pins VDD must be directly connected to each other. Also all pins GND must be directly connected to each other. To keep VDD and GND bounce to a minimum a bypass capacitor (10 nF to 100 nF) should be placed between each pair of VDD/GND pins.
2.10
RESET characteristics
The reset signal (hardware reset or software reset) must be active for at least 4 clock cycles. The GCI/IOM2 bus lines STIO1, STIO2 and the interrupt lines are in tristate mode after a reset. The HFC-S PCI is in slave mode after reset. C4IO and F0IO are inputs. The S/T state machine is stuck to '0' after reset. This means the HFC-S PCI does not react to any signal on the S/T interface before the S/T state machine is initialised. The registers' initial values are described in the Register bit description (section 4 of this data sheet). During initialisation phase the HFC-S PCI must not be accessed. Bit 1 of the STATUS register is cleared to '0' to indicate that the initialisation phase has been finished.
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3
3.1 3.1.1
Functional description
PCI-interface PCI access types used by HFC-S PCI C/BE2# 0 0 1 1 0 0 C/BE1# 1 1 1 1 1 1 C/BE0# 0 1 0 1 0 1 Command Type I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write HFC-S PCI mode target mode target mode target mode and master mode target mode and master mode target mode target mode
C/BE3# 0 0 0 0 1 1
Table 1: PCI command types
3.1.2
PCI modes supported
The HFC-S PCI supports both target mode and master mode. Before the HFC-S PCI can operate in master mode the 32K Memory Window Base Address register (MWBA) must be configured. Afterwards all FIFO data accesses are done by the HFC-S PCI automatically by PCI master accesses. Only control and configuration register accesses must be done by PCI target accesses by the host CPU.
3.1.3 PCI buffer signaling and power supply environment The HFC-S PCI supports 5V and 3.3V PCI bus environments. The environment mode is set during RESET (RST# low) by the input value of /ADR_WR. PCI bus power and signaling environment 3.3V 5V
*)
/ARD_WR during RST# low high *) low
external pull-up resistor required (10k)
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3.1.4
PCI configuration registers
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The external EEPROM is optional. If no EEPROM is available, EE_SCL/EN must be connected to GND. Without EEPROM the PCI configuration registers will be loaded with the default values shown in Table 2. All registers which can be read from EEPROM can also be written by configuration write accesses. The addresses for configuration write are shown in the table below. Register Name Vendor ID Device ID Command Register Default Value 1397h 2BD0h Remarks Value can be read from EEPROM. Base address for configuration write is C0h. Value can be read from EEPROM. Base address for configuration write is C0h. Bits Function 0 Enables/disables I/O space accesses. 1 Enables/disables memory space accesses. 2 Enables/disables master accesses. 5..3 fixed to '0' 6 PERR# enable/disable 7 fixed to '0' 8 SERR# enable/disable 15..9 fixed to '0' Bits[7:0] can be read from EEPROM. Base address for configuration write is C4h. Bits Function 3..0 reserved 4 fixed to '1' 5 66MHz capable 6 User definable features supported 7 fast Back-to-Back capable 8 data parity error detected 10..9 fixed to '01': timing of DEVSEL# is medium 11 signaled target abort (fixed to '0') 12 received target abort 13 received master abort 14 signaled system error (Addr. parity error) 15 detected partity error Value can be read from EEPROM. Base address for configuration write is C8h. Set to 16 clocks, value is fixed. Header Type 0 No build in self test supported. Bits[31:3] are r/w by configuration accesses Bits[31:8] are r/w by configuration accesses Value can be read from EEPROM. Base address for configuration write is ECh. Value can be read from EEPROM. Base address for configuration write is ECh. Offset to Power Management register block.
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Status Register
0210h
Revision ID Class Code Latency Timer Header Type BIST I/O Base Address Memory Base Address Subsystem Vendor ID Subsystem ID Cap_Ptr
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01h 02 80 00h 10h 00h 00h
1397h 2BD0h 40h
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Register Name Interrupt Line Interrupt Pin Min_Gnt Max_Lat Cap_ID Next Ptr PMC
Default Value FFh 01h 00h 10h 01h 00h 7E21h
PMCSR
0000h
Remarks This register must be configured by configuration write. INTA supported Value can be read from EEPROM. Base address for configuration write is FCh. Value can be read from EEPROM. Base address for configuration write is FCh. Capability ID. 01h identifies the linked list item as PCI Power Management registers. There are no next items in the linked list. Power Management Capabilities. See also PCI Bus Power Management Interface Specification. This register's value can be read from EEPROM. Base address for configuration write is E0h. PME# can be asserted from D0, D1, D2 and D3hot. Device specific initialisation is required. The HFC-S PCI does not require PCI-clock to generate PME# (if S/T change state is selected). This function complies with the PCI Power Management Spec. Version 1.0. Power Management Control/Status Bits Function 15 PME_Status - This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. Writing a '1' to this bit will clear it and cause the function to stop asserting a PME# (if enabled). Writing a '0' has no effect. 14..9 fixed to '0' 8 PME_En - A '1' enables the function to assert PME#. When '0', PME# assertion is disabled. 7..2 fixed to '0' 1..0 PowerState - This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. 00b - D0 01b - D1 10b - D2 11b - D3hot All States except D0 disable HFC-S PCI master accesses.
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Register Name 32K Memory Window Base Address (MWBA)
Default Value 0000h
Remarks Bits[31:15] are r/w by configuration accesses. The 32K Memory Window is for HFC-S PCI internal use and for the B- and D-channel FIFOs. This register must be written by a "DWORD Config Write" to enable the HFC-S PCI to operate in master mode.
Table 2: PCI configuration registers' initial values Unimplemented registers return all 0's when read.
3.2
Internal HFC-S PCI register description
If the HFC-S PCI is used in memory mapped mode all register can directly be accessed by adding their CIP address to the configured Memory Base Address. In I/O address mapped mode the HFC-S PCI occupies 8 bytes in the I/O address space. Byte 0 is for data read/write, byte 4 for register selection. The AUX-port address is selected by byte 3, AUX-port data is read/written by byte 1.
Figure 3: HFC-S PCI in I/O address mapped mode
Figure 4: HFC-S PCI in memory address mapped mode
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3.2.1
Registers of the S/T section Name STATES SCTRL SCTRL_E SCTRL_R SQ_REC SQ_SEND CLKDEL r/w r/w w w w r w w Function State of the TE/NT state machine S/T control register S/T control register (extended) receive enable for B-channels receive register for S/Q bits send register for S/Q bits setup of the delay time between receive and send direction (TE) receive data sample time (NT) B1-channel receive register B1-channel transmit register B2-channel receive register B2-channel transmit register D-channel receive register D-channel transmit register E-channel receive register
CIP / I/O-address 1100 0000 1100 0100 1100 1000 1100 1100 1101 0000 C0h C4h C8h CCh D0h
1101 1100
DCh
1111 0000
F0h
B1_REC*) B1_SEND*) B2_REC*) B2_SEND*) D_REC*) D_SEND*) E_REC*)
r w r w r w r
1111 0100
F4h
1111 1000
F8h
1111 1100
FCh
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or GCI/IOM2 bus controller and need not be accessed by the user. To read/write data the FIFOs in the Memory Window should be used.
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3.2.2
Registers of the GCI/IOM2 bus section
GCI/IOM2 bus timeslot selection registers CIP / I/O-address 0000 1000 0000 1100 0010 1000 0010 1100 08h 0Ch 28h 2Ch Name C/I TRxR MON1_D MON2_D r/w r/w r r/w r/w Function C/I command/indication register Monitor Tx ready handshake first monitor byte second monitor byte
GCI/IOM2 bus timeslot selection registers CIP / I/O-address 1000 0000 1000 0100 1000 1000 1000 1100 1001 0000 1001 0100 1001 1000 1001 1100 80h 84h 88h 8Ch 90h 94h 98h 9Ch Name B1_SSL B2_SSL AUX1_SSL AUX2_SSL B1_RSL B2_RSL AUX1_RSL AUX2_RSL r/w w w w w w w w w Function B1-channel transmit slot (0..31) B2-channel transmit slot (0..31) AUX1-channel transmit slot (0..31) AUX2-channel transmit slot (0..31) B1-channel receive slot (0..31) B2-channel receive slot (0..31) AUX1-channel receive slot (0..31) AUX2-channel receive slot (0..31)
GCI/IOM2 bus data registers CIP / I/O-address 1010 0000 1010 0100 1010 1000 1010 1100 A0h A4h A8h ACh Name B1_D*) B2_D*) AUX1_D AUX2_D r/w r/w r/w r/w r/w Function GCI/IOM2 bus B1-channel data register GCI/IOM2 bus B2-channel data register AUX1-channel data register AUX2-channel data register
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or by the S/T controller and need not be accessed by the user.
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GCI/IOM2 bus configuration registers CIP / I/O-address 1011 0100 1011 1000 1011 1100 B4h B8h BCh Name r/w Function extended mode register for GCI/IOM2 bus mode register for GCI/IOM2 bus connect functions for S/T, HFC, GCI/IOM2
MST_EMOD w MST_MODE w CONNECT w
3.2.3
Interrupt and status registers Name FIFO_EN TRM B_MODE CHIP_ID CIRM CTMT r/w w w w r w w Function FIFO enable/disable transparent mode interrupt mode register mode of B-channels register for chip identification interrupt selection and softreset register transparent mode and timer control register
CIP / I/O address 0100 0100 0100 1000 0100 1100 0101 1000 0110 0000 0110 0100 44h 48h 4Ch 58h 60h 64h
0110 1000 0110 1100
68h 6Ch
INT_M1 INT_M2
w w
interrupt mask register 1 interrupt mask register 2
0111 1000 0111 1100
78h 7Ch
INT_S1 INT_S2
r r
interrupt status register 1 interrupt status register 2
0111 0000
70h
STATUS
r
common status register
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3.3
Timer
The HFC-S PCI includes a timer with interrupt capability. The timer counts F0IO pulses. So the timer counter is incremented every 125s. It can be reset by bit 7 of of the CTMT register. Furthermore the timer is reset at every HFC-S PCI access when bit 5 of the CTMT register is set. Seven different timer values can be selected.
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3.4
FIFOs
All FIFOs are located in the 32K Memory Window (MW) in host PC's memory. There are 6 FIFOs with 6 HDLC-Controllers handled by the HFC-S PCI. The HDLC circuits are located on the S/T device side of the HFC-S PCI. So always plain data is stored in the FIFO. Zero insertion and deletion is done in HDLC mode: - if the data goes to the S/T or GCI/IOM device in send FIFOs and - when the HDLC data comes from the S/T device or GCI/IOM2 bus in receive operation. There are a send and a receive FIFO for each of the two B-channels and for the D-channel. The FIFOs are realized as ring buffers in the 32K Memory Window in host PC's memory. To control them there are some counters. B-channel 13 Bit 13 Bit D-channel 9 Bit 9 Bit
Z1: FIFO input counter Z2: FIFO output counter
Each counter points to a byte position in the Memory Window. This is an offset to the 32K Memory Window Base Address in the configuration space. On a FIFO input operation Z1 is incremented. On an output operation Z2 is incremented. After every pulse on the F0IO signal two HDLC-bytes are written into the S/T interface (FIFOs No. 0 and 2) and two HDLC-bytes are read from the S/T interface (FIFOs No. 1 and 3). D-channel data is handled in a similar way but only 2 bits are processed.
* important!
Instead of the S/T interface also GCI/IOM2 bus is selectable for each B-channel (see CONNECT register). If Z1 = Z2 the FIFO is empty. Additionally there are two counters F1 and F2 for every FIFO channel (5Bit for B-channel, 4Bit for Dchannel). They count the HDLC-frames in the FIFOs and form a ring buffer as Z1 and Z2 do, too. F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is incremented when a complete frame has been read from the FIFO. If F1 = F2 there is no complete frame in the FIFO. When the RESET line is active or software reset is active Z1, Z2, F1 and F2 are all initialized to all 1s. All Zx and Fx counters are also stored in the Memory Window. So it is easy to read and write the counters by simple host memory accesses.
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Because the HFC-S PCI is limited to the 32K Memory Window data in different regions of the host PC can not be overwritten even if counter and pointer values are handled in a wrong way.
* important!
The counter state 0200h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs. The counter state 000h of the Z-counters follows counter state 1FFh in the D-channel FIFOs. The counter state 00h of the F-counters follows counter state 1Fh in the B-channel FIFOs. The counter state 10h of the F-counters follows counter state 1Fh in the D-channel FIFOs.
3.4.1
FIFO counters location in Memory Window
For each FIFO one F1 and one F2 counter is available. The counters are located at the following offsets to the Memory Window Base Address (MWBA) in the Memory Window (MW). FIFO B1-transmit B1-receive B2-transmit B2-receive D-transmit D-receive Counter F1 F2*) F1*) F2 F1 F2*) F1*) F2 F1 F2*) F1*) F2 Offset to Memory Window Base Address 2080h 2081h 6080h 6081h 2180h 2181h 6180h 6181h 20A0h 20A1h 60A0h 60A1h Counter Size in Bytes 1 1 1 1 1 1 1 1 1 1 1 1
*)
These counters are handled by the HFC-S PCI automatically and must not be written by software.
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For each FIFO an array of Z1 and Z2 counters is available. The offset of the counters to the Memory Window Base Address (MWBA) can be calculated as shown in the following table. FIFO B1-transmit B1-receive B2-transmit B2-receive D-transmit D-receive Counter Z1 Z2*) Z1*) Z2 Z1 Z2*) Z1*) Z2 Z1 Z2*) Z1*) Z2 Offset to Memory Window Base Address 2000h + (Fx * 4) 2000h + (Fx * 4) + 2 6000h + (Fx * 4) 6000h + (Fx * 4) + 2 2100h + (Fx * 4) 2100h + (Fx * 4) + 2 6100h + (Fx * 4) 6100h + (Fx * 4) + 2 2080h + (Fx * 4) 2080h + (Fx * 4) + 2 6080h + (Fx * 4) 6080h + (Fx * 4) + 2 Counter Size in Bytes 2 2 2 2 2 2 2 2 2 2 2 2
*)
These counters are handled by the HFC-S PCI automatically and must not be written by software.
Fx is either F1 or F2. F1 is used for input data in transmit FIFOs, F2 is used for output data in receive FIFOs.
3.4.2 FIFO
FIFO data location in Memory Window Starting at Offset 0200h 4200h 2200h 6200h 0000h 4000h Ending at Offset 1FFFh 5FFFh 3FFFh 7FFFh 01FFh 41FFh Offset to add to Z-counters value 0000h 4000h 2000h 6000h 0000h 4000h
B1-transmit B1-receive B2-transmit B2-receive D-transmit D-receive
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3.4.3
FIFO channel operation
Figure 5: FIFO Organisation (shown for B-channel, similar for D-channel)
3.4.3.1 Send channels (B1, B2 and D transmit) The send channels send data from the host bus interface to the FIFO and the HFC-S PCI converts the data into HDLC code and tranfers it from the FIFO into the S/T or/and the GCI/IOM2 bus interface write registers. The HFC-S PCI checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-S PCI generates a HDLC-Flag (01111110) and sends it to the S/T device. In this case Z2 is not incremented. If also F1=F2 only HDLC flags are sent to the S/T interface and all counters remain unchanged. If the frame counters are unequal F2 is incremented and the HFC-S PCI tries to send the next frame to the output device. After the end of a frame (Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds the ending flag. If there is another frame in the FIFO (F1F2) the F2 counter is incremented. With every byte being sent from the host bus side to the FIFO Z1 is incremented automatically. If a complete frame has been sent F1 must be incremented to send the next frame. If the frame counter F1 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 5). Z1(F1) is used for the frame which is just written from the PC-bus side. Z2(F2) is used for the frame which is just beeing transmitted to the S/T device side of the HFC-S PCI. Z1(F2) is the end of frame pointer of the current output frame.
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In the send channels F1 is only changed from the PC interface side if the software driver wants to say end of send frame". Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start address of the next frame. Z1(F2) and Z2(F2) can not be accessed.
3.4.3.2 Automatically D-channel frame repetition The D-channel send FIFO has a special feature. If the S/T interface signals a D-channel contention before the CRC is sent the Z2 counter is set to the starting address of the current frame and the HFC-S PCI tries to repeat the frame automatically.
* important!
The HFC-S PCI begins to transmit bytes from a FIFO at the moment Z1 Z2. So if the Z1 pointer is updated by software after writing the transmit data into the FIFO space of the Memory Window the transmission starts.
3.4.3.3 FIFO full condition in send channels FIFO full condition can easily be calculated from the Z1/Z2 table in the Memory Window. Remember that an increment of Z-value 1FFFh is 0200h in the B-channels! There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 31 frames (B-channel) or 15 frames (D-channel). There is no possibility for the HFC-S PCI to manage more frames even if the frames are very small. The second limitation is the size of the FIFO which is 512 byte for the D-channel and 7.5 KByte for the B-channels.
3.4.3.4 Receive Channels (B1, B2 and D receive) The receive channels receive data from the S/T or GCI/IOM2 bus interface read registers. The data is converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host bus interface. The HFC-S PCI checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is converted by the HFC-S PCI into plain data. After the ending flag of a frame the HFC-S PCI checks the HDLC CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO named STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC field at the end of the frame.
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Figure 6: FIFO Data Organisation The ending flag of a HDLC-frame can also be the starting flag of the next frame. After a frame is received completely F1 is incremented by the HFC-S PCI automatically and the next frame can be received. After reading a frame via the host bus interface F2 must be incremented. If the frame counter F2 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 5). Z1(F1) is used for the frame which is just received from the S/T device side of the HFC. Z2(F2) is used for the frame which is just beeing transmitted to the host bus interface. Z1(F2) is the end of frame pointer of the current output frame. To calculate the length of the current receive frame the software has to evaluate Z1-Z2+1. In the receive channels F2 must be incremented to point to the next Z1/Z2 pair. If Z1 = Z2 and F1 = F2 the FIFO is totally empty.
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3.4.3.5 FIFO full condition in receive channels Because the ISDN-B-channels and the ISDN-D-channels have no hardware based flow control there is no possibility to stop input data if a receive FIFO is full. So there is no FIFO full condition implemented in the HFC-S PCI. The HFC-S PCI assumes that the FIFOs are so deep that the host processor hard- and software is able to avoid any overflow of the receive FIFOs. Overflow conditions are again more than 31 input frames (15 frames for D-channel) or a real overflow of the FIFO because of excessive data. Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent without software intervention. Due to the great size of the FIFOs of the HFC-S PCI it is easy to poll counters in the Memory Window even in large time intervalls without having to fear a FIFO overflow condition. However to avoid any undetected FIFO overflows the software driver should check the number of frames in the FIFO which is F1-F2. An overflow exists if the number (F1-F2) is less than the number in the last reading even if there was no reading of a frame in between. After a detected FIFO overflow condition this FIFO must be reset.
3.4.3.6 FIFO initialisation All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET. Then the result is Z1 = Z2 = 1FFFh and F1 = F2 = 1Fh for the B-channels and Z1 = Z2 = 1FFh and F1 = F2 = 1Fh for the D-channel. This information is written in the Memory Window for initialisation. Please mask bit 4 of D-channel from counter F1, F2. The same initialisation is done if the bit 3 in the CIRM register is set (soft reset). During initialisation phase the HFC-S PCI must not be accessed. Bit 1 of the STATUS register is cleared to '0' to indicate that the initialisation phase has been finished.
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3.4.4
Transparent mode of HFC-S PCI
You can switch off HDLC operation for each B-channel independently. There is one bit for each Bchannel in the CTMT control register. If this bit is set data in the FIFO is sent directly to the S/T or GCI/IOM2 bus interface and data from the S/T or GCI/IOM2 bus interface is sent directly to the FIFO. Be sure to switch into transparent mode only if F1=F2. Being in transparent mode the Fx counters remain unchanged. Z1 and Z2 are the input and output pointers respectively. Because F1=F2 both Z-counters are always accessable and have valid data. If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte written into the FIFO is repeated until there is new data. In receive channels there is no check on flags or correct CRCs and no status byte is added. The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved with HDLC-flags. The data is just the same as it comes from the S/T or GCI/IOM2 bus interface or is sent to this. Send and receive transparent data can be handled in two ways. The usual way is transmitting B-channel data with the LSB first as it is usual in HDLC mode. The second way is sending the bytes in reverse bit order as it is usual for PWM data. So the first bit is the MSB. The bit order can be reversed by setting the corresponding bits in the CIRM register.
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4
4.1
Register bit description
Register bit description of S/T section Addr. C0h Bits 3..0 4 r/w r w w Function binary value of actual state (NT: Gx, TE: Fx) prepare for new state xxxx '1' loads the prepared state (bit 3..0) and stops the state machine.This bit needs to be set for a minimum period of 5.21Ps and must be cleared by software. (reset default) '0' enables the state machine. After writing an invalid state the state machine goes to deactivated state (G1, F2) '0' prepare deactivation '1' prepare activation '1' start activation/deactivation as selected by bit 5 This bit is automatically cleared after activation/deactivation. '0' no operation '1' in NT mode allows transition from G2 to G3. This bit is automatically cleared after the transition.
Name STATES
5 6 7
w w w
* important!
The state machine is stuck to '0' after a reset. Writing a '0' to bit 4 of the STATES register restarts the state machine. In this state the HFC-S PCI sends no signal on the S/T-line and it is not possible to activate it by incoming INFOx. NT mode: The NT state machine does not change automatically from G2 to G3 if the TE side sends INFO3 frames. This transition must be activated each time by bit 7 of the STATES register.
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Name SCTRL
Addr. C4h
Bits 0
1
2
3
4
5 6
7
SCTRL_E
C8h
0
1 2
3
6..4 7
r/w Function B-channel enable w '0' B1 send data disabled (permanent 1 sent in activated states, reset default) '1' B1 data enabled w '0' B2 send data disabled (permanent 1 sent in activated states, reset default) '1' B2 data enabled w S/T interface mode '0' TE mode (reset default) '1' NT mode w D-channel priority '0' high priority 8/9 (reset default) '1' low priority 10/11 w S/Q bit transmission '0' S/Q bit disable (reset default) '1' S/Q bit and multiframe enable w '0' normal operation (reset default) '1' send 96kHz transmit test signal (alternating zeros) w TX_LO line setup This bit must be configured depending on the used S/T module and circuitry to match the 400 pulse mask test. '0' capacitive line mode (reset default) '1' non capacitive line mode w Power down '0' power up, oscillator active (reset default) '1' power down, oscillator stopped w Power down mode bit '0' S/T awake disable (reset default) Power up can only be programmed by register access (SCTRL bit 7). '1' S/T awake enable. Oscillator starts on every non INFO0 S/T signal. w must be '0' w D reset '0' normal operation (reset default) '1' D bits are forced to '1' w D_U enable '0' normal operation (reset default) '1' D channel is always send enabled regardless of E receive bit w must be '0' w '0' normal operation (reset default) '1' B1/B2 are exchanged in the S/T interface
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Name SCTRL_R
Addr. CCh
Bits 0 1
SQ_REC
D0h
7..2 3..0
4 6..5 7 SQ_SEND D0h 3..0
CLKDEL
DCh
7..4 3..0
6..4
7
r/w Function w B1-channel receive enable w B2-channel receive enable '0' B-receive bits are forced to '1' '1' normal operation w unused r TE mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) NT mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) r '1' a complete S or Q multiframe has been received Reading SQ_REC clears this bit. r not defined r '1' ready to send a new S or Q multiframe Writing to SQ_SEND clears this bit. w TE mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) NT mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) w not defined w TE: 4 bit delay value to adjust the 2 bit delay time between receive and transmit direction. The delay of the external S/T-interface circuit can be compensated. The lower the value the smaller the delay between receive and transmit direction (see also Figure 14) NT: Data sample point. The lower the value the earlier the input data is sampled. The steps are 163ns. w NT mode only early edge input data shaping Low pass characteristic of extended bus configurations can be compensated. The lower the value the earlier input data pulse is sampled. No compensation means a value of 6 (110b). Step size is the same as for bits 3-0. w unused
* note!
The register is not initialized with a '0' after reset. The register should be initialized as follows before activating the TE/NT state machine: TE mode: 0Dh .. 0Fh NT mode: 6Ch
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4.2
Register bit description of GCI/IOM2 bus section
Timeslots for transmit direction Name B1_SSL B2_SSL AUX1_SSL AUX2_SSL Addr. 80h 84h 88h 8Ch Bits 4..0 5 6 r/w w w w Function select GCI/IOM2 bus transmission slot (0..31) unused select GCI/IOM2 bus data lines '0' STIO1 output '1' STIO2 output transmit channel enable for GCI/IOM2 bus '0' disable (reset default) '1' enable
7
w
* important!
Enabling more than one channel on the same slot causes undefined output data.
Timeslots for receive direction Name B1_RSL B2_RSL AUX1_RSL AUX2_RSL Addr. 90h 94h 98h 9Ch Bits 4..0 5 6 r/w w w w Function select GCI/IOM2 bus receive slot (0..31) unused select GCI/IOM2 bus data lines '0' STIO2 is input '1' STIO1 is input receive channel enable for GCI/IOM2 bus '0' disable (reset default) '1' enable
7
w
Data registers Name B1_D B2_D AUX1_D AUX2_D Addr. A0h A4h A8h ACh Bits 0..7 r/w Function r/w read/write data registers for selected timeslot data
* note!
If the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots AUX1_SSL and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots. This is useful for an internal connection between two CODECs. This mirroring is disabled by setting bit 1 in MST_EMOD register
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Name MST_MODE
Addr. B8h
Bits 0
1
2
3
5, 4
7, 6
r/w Function w GCI/IOM2 bus mode '0' slave (reset default) (C4IO and F0IO are inputs) '1' master (C4IO and F0IO are outputs) w polarity of C4- and C2O-clock '0' F0IO is sampled on negative clock transition '1' F0IO is sampled on positive clock transition w polarity of F0-signal '0' F0 positive pulse '1' F0 negative pulse w duration of F0-signal '0' F0 active for one C4-clock (244ns) (reset default) '1' F0 active for two C4-clocks (488ns) w time slot for codec-A signal F1_A '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' signal C2O pin F1_A (C2O is 2048 kHz clock) w time slot for codec-B signal F1_B '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' AUX2 receive slot
The pulse shape and polarity of the codec signals F1_A and F1_B is the same as the pulseshape of the F0IO signal. The polatity of C2O can be changed by bit 1. RESET sets register MST_MODE to all '0's.
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Name MST_EMOD
Addr. B4h
Bits 0
1
2 5..3
6 7
C/I
08h
3..0 7..4 0 1 5..2 6 7
TRxR
0Ch
r/w Function w slow down C4IO clock adjustment (see Figure 17) '0' C4IO clock is adjusted in the 31th time slot twice for one half clock cycle (reset default) '1' C4IO clock is adjusted in the 31th time slot once for one half clock cycle w enable/disable AUX channel mirroring '0' normal opration (reset default) '1' disable AUX channel data mirroring w unused w select D-channel data flow (see also: CONNECT register) destination source bit 3: '0' D-HFC D-S/T '1' D-HFC D-GCI/IOM2 bit 4: '0' D-S/T D-HFC '1' D-S/T D-GCI/IOM2 bit 5: '0' D-GCI/IOM2 D-HFC '1' D-GCI/IOM2 D-S/T w unused w enable GCI/IOM2 write slots '0' disable GCI/IOM2 write slots; slot #2 and slot #3 may be used for normal data '1' enables slot #2 and slot #3 as master, D- and C/I-channel r/w on read: indication on write: command unused r '1' monitor receive ready (2 bytes received) This bit is reset after read of second monitor byte (MON2_D) r '1' Monitor transmitter ready Writing on MON2_D starts transmisssion and resets this bit. r reserved r STIO2 in r STIO1 in
RESET sets register MST_EMOD to all '0's.
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4.3
Register bit description of CONNECT register Addr. BCh Bits 2..0 r/w Function w select B1-channel data flow destination bit 0: '0' B1-HFC '1' B1-HFC bit 1: '0' B1-S/T '1' B1-S/T bit 2: '0' B1-GCI/IOM2 '1' B1-GCI/IOM2 w select B2-channel data flow destination bit 3: '0' B2-HFC '1' B2-HFC bit 4: '0' B2-S/T '1' B2-S/T bit 5: '0' B2-GCI/IOM2 '1' B2-GCI/IOM2 w unused
Name CONNECT

source B1-S/T B1-GCI/IOM2 B1-HFC B1-GCI/IOM2 B1-HFC B1-S/T source B2-S/T B2-GCI/IOM2 B2-HFC B2-GCI/IOM2 B2-HFC B2-S/T
5..3
7..6
RESET sets CONNECT register to all '0's. The following figure shows the different options for switching the B-channels with the CONNECT register.
Figure 7: Function of the CONNECT register bits
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4.4 Name CIRM
Register bit description of auxiliary and cross data registers Addr. 60h Bits 2..0 r/w Function w defines the length of the auxiliary port access: Value Cycle time (AUX_WR or AUX_RD low) 000b 1 PCI-Clock 001b 3 PCI-Clocks 010b 5 PCI-Clocks 011b 7 PCI-Clocks 100b 9 PCI-Clocks 101b 11 PCI-Clocks 110b 13 PCI-Clocks 111b 15 PCI-Clocks w soft reset, similar as hardware reset; the registers CIP, CIRM and CTMT are not changed. The PCI interface is not reset. The reset is active until the bit is cleared. '0' deactivate reset (reset default) '1' activate reset w must be '0' w select bit order for B1 channel '0' normal read/write data operation '1' reverse bit order read/write data operation w select bit order for B2 channel '0' normal read/write data operation '1' reverse bit order read/write data operation w FIFO enable/disable ('1' = enable (reset default)) Bit FIFO 0 B1-transmit 1 B1-receive 2 B2-transmit 3 B2-receive 4 D-transmit 5 D-receive The enable/disable change becomes valid between 0 and 250s after the bit has been written. All PCI bus accesses and FIFO activities are disabled for the selected FIFOs. To avoid unnecessary PCI transfers all unused FIFOs should be disabled. At least one FIFO (usually D-receive) must be enabled. w unused, should be '0'
3
5..4 6
7
FIFO_EN
44h
5..0
7..6
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Name CTMT
Addr. 64h
Bits 0
1
4..2
5
6 7
CHIP_ID
58h
0
3..1 7..4 B_MODE 4Ch 1..0 2 3 4
5
6 7
r/w Function w HDLC/transparent mode for B1-channel '0' HDLC mode (reset default) '1' transparent mode w HDLC/transparent mode for B2-channel '0' HDLC mode (reset default) '1' transparent mode w select timer (bit 4 = MSB) timer '000' off '001' 3.125ms '010' 6.25ms '011' 12.5ms '100' 25ms '101' 50ms '110' 400ms '111' 800ms w timer reset mode '0' reset timer by CTMT bit 7 (reset default) '1' automatically reset timer at each access to HFC-S PCI w ignored w reset timer '1' reset timer This bit is automatically cleared. r power supply '0' 5V PCI signaling environment '1' 3.3V PCI signaling environment r reserved r Chip identification 0011b HFC-S PCI w unused w in 64 kbit/s mode: bit is ignored in 56 kbit/s mode: value of the LSB in 7-bit mode w unused w 56 kbit/s mode selection bit for B1-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode w 56 kbit/s mode selection bit for B2-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode w '0' Data not inverted for B1-channel (reset default) '1' Data inverted for B1-channel w '0' Data not inverted for B2-channel (reset default) '1' Data inverted for B2-channel
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Name INT_M1
Addr. 68h
Bits 0 1 2 3 4 5 6 7
r/w w w w w w w w w
Function interrupt mask for channel B1 in transmit direction interrupt mask for channel B2 in transmit direction interrupt mask for channel D in transmit direction interrupt mask for channel B1 in receive direction interrupt mask for channel B2 in receive direction interrupt mask for channel D in receive direction interrupt mask for state change of TE/NT state machine interrupt mask for timer
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'. Name INT_M2 Addr. 6Ch Bits 0 1 2 3 6..4 7 r/w w w w w w w Function interrupt mask for processing/non processing phase transition interrupt mask for GCI I-change interrupt mask for GCI monitor receive enable for interrupt output ('1' = enable) unused PMESEL '0' PME triggered on D-channel receive int '1' PME triggered on S/T interface state change
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'. Name TRM Addr. 48h Bits 1..0 r/w Function w interrupt in transparent mode is generated if Z1 in receive FIFOs or Z2 in transmit FIFOs change from: 00: x xxxx x011 1111 x xxxx x100 0000 01: x xxxx 0111 1111 x xxxx 1000 0000 10: x xxx0 1111 1111 x xxx1 0000 0000 11: x 0111 1111 1111 x 1000 0000 0000 w must be '0' w E B2 receive channel When set the E receive channel of the S/T interface is connected to the B2 receive channel. w B1+B2 mode '0' normal operation (reset default) '1' B1+B2 are combined to one HDLC or transparent channel. All settings for data shape and connect are derived from B1. w IOM test loop When set MST output data is looped to the MST input.
4..2 5
6
7
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Name INT_S1
Addr. 78h
Bits 0 1
2
3 4
5
6 7 INT_S2 7Ch 0
1 2 6..3 7
r/w Function r B1-channel interrupt status in transmit direction r B2-channel interrupt status in transmit direction in HDLC mode: '1' a complete frame has been transmitted, the frame counter F2 has been incremented in transparent mode: '1' interrupt as selected in TRM register bits 1..0 r D-channel interrupt status in transmit direction '1' a complete frame was transmitted, the frame counter F2 was incremented r B1-channel interrupt status in receive direction r B2-channel interrupt status in receive direction in HDLC mode: '1' a complete frame has been transmitted, the frame counter F1 has been incremented in transparent mode: '1' interrupt as selected in TRM register bits 1..0 r D-channel interrupt status in receive direction '1' a complete frame was received, the frame counter F1 was incremented r TE/NT state machine interrupt status '1' state of state machine changed r timer interrupt status '1' timer is elapsed r processing/non processing transition interrupt status '1' The HFC-S PCI has changed from processing to non processing state. r GCI I-change interrupt '1' a different I-value on GCI was detected r receiver ready (RxR) of monitor channel '1' 2 monitor bytes have been received r unused, '0' r '1' fatal error: synchronisation lost. PCI performance too low for HFC-S PCI. Only soft reset recovers from this situation.
* important!
Reading the INT_S1 or INT_S2 register resets all active read interrupts in the INT_S1 or INT_S2 register. New interrupts may occur during read. These interrupts are reported at the next read of INT_S1 or INT_S2. All interrupt bits are reported regardless of the mask registers settings (INT_M1 and INT_M2). The mask register settings only influence the interrupt output condition. The interrupt output goes inactive during the read of INT_S1 or INT_S2. If interrupts occur during this read the interrupt line goes active immediately after the read is finished. So processors with level or transition triggered interrupt inputs can be connected.
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Name STATUS
Addr. 70h
Bits 0 1
2
3 4
5 6 7
r/w Function r always '0' r processing/non processing status '1' the HFC-S PCI is in processing phase (every 125s) '0' the HFC-S PCI is not in processing phase r processing/non processing transition interrupt status '1' The HFC-S PCI has finished internal processing phase (every 125s) r always '0' r timer status '0' timer not elapsed '1' timer elapsed r TE/NT state machine interrupt state '1' state of state machine has changed r FRAME interrupt has occured (any data channel interrupt) all masked D-channel and B-channel interrupts are "ored" r ANY interrupt all masked interrupts are "ored"
Reading the STATUS register clears no bit.
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5
Electrical characteristics
Symbol VDD VI VO Topr Tstg Rating -0.3V to +7.0V -0.3V to VDD + 0.3V -0.3V to VDD + 0.3V -10C to +85C -40C to +125C
Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature
Recommended operating conditions Parameter Supply voltage Operating temperature Symbol VDD Topr Condition VDD=5V VDD=3.3V MIN. 4.75V 3.15V 0C TYP. 5.0V 3.3V MAX. 5.25V 3.45V +70C
Electrical characteristics for 5V power supply
VDD = 4.75V to 5.25V, Topr = 0C to +70C
Parameter Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage Output leakage current Pull-up resistor input current
Symbol VIL VIH VOL VOH | IOZ | | IIL |
Condition
High Z VI = VSS
TTL level MIN. TYP. MAX. 0.8V 2.0V 0.4V 4.3V 10A 50A
CMOS level MIN. TYP. MAX. 1.0V 3.5V 0.4V 4.3V 10A 50A
Electrical characteristics for 3.3V power supply
VDD = 3.15V to 3.45V, Topr = 0C to +70C
Parameter Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage
Symbol VIL VIH VOL VOH
Condition MIN. 2.0V
TTL level TYP. MAX. 0.8V 0.4V
2.4V
CMOS level MIN. TYP. MAX. 1.0V 2.3V 0.4V 2.4V
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DC current consumption of HFC-S PCI
25C ambient temperature, 5 V operating voltage, 33 MHz PCI clock
Condition PCI master, PCM master (full operational) power down, no S/T awake (12.288 MHz OSC off) All pins GND (except power supply)
MIN.
TYP. 24,5 mA 15 mA
MAX.
1 mA
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I/O Characteristics Input AD0-31 PAR C/BE0-3 RST# FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# GNT# PERR# DAUX0-7 C4IO F0IO STIO1-2 EE_SDA EE_SCL/EN Interface Level PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI TTL TTL, internal pull-up resistor TTL, internal pull-up resistor TTL, internal pull-up resistor TTL, internal pull-up resistor TTL, internal pull-up resistor
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Driver Capability Low Output AD0-31 PAR
*) *) *) *)
High 0.6V VDD - 0.4V 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 1mA 3mA 2mA 1mA 1mA 4mA 3mA 3mA 2mA 3mA 3mA 0.5mA 4mA 4mA 4mA 3mA 0.5mA 0.5mA
0.4V 6mA 6mA 6mA 6mA 6mA 6mA 6mA
C/BE0-3 IRDY# STOP# REQ#
FRAME#
*) *)
TRDY#
*) *)
DEVSEL#
*) *) *)
6mA 6mA 6mA 6mA 2mA 6mA 4mA 2mA 2mA 8mA 6mA 6mA 4mA 6mA 6mA 1mA 8mA 8mA 8mA 6mA 1mA
PERR# SERR# PME INTA#
*)
DAUX0-7 /AUX_WR /AUX_RD /ADR_WR TX2_HI /TX1_LO /TX_EN /TX2_LO TX1_HI ADJ_LEV C4IO F0IO STIO1-2 F1_A-B EE_SDA
*)
EE_SCL/EN 1mA PCI buffer is PCI Spec. 2.1 compliant.
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6
6.1
Timing characteristics
PCI bus timing
The timing characteristics of the HFC-S PCIs integrated PCI bus interface is compliant with version 2.1 of the PCI Local Bus specification.
6.2
GCI/IOM2 bus clock and data alignment for Mitel STTM bus
Figure 8: GCI/IOM2 bus clock and data alignment
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6.3
GCI/IOM2 timing
Timing diagram 1: GCI/IOM2 timing
*)
F0IO starts one C4IO clock earlier if bit 3 in MST_MODE register is set. If this bit is set F0IO is also awaited one C4IO clock cycle earlier.
SYMBOL tC4P tC4H tC4L tC2P tC2H tF0iS tF0iH tF0iW tSToD
CHARACTERISTICS Clock C4IO period (4.096 MHz) Clock C4IO High Width Clock C4IO Low Width Clock C2O Period Clock C2O High Width F0IO Setup Time F0IO Hold Time F0IO Width STIO1 Delay Level 1 Output
MIN. 243.9 ns 110 ns 110 ns 487.8 ns 220 ns 50 ns 50 ns 200 ns 20 ns
MAX 244.4 ns 134 ns 134 ns 488.8 ns 268 ns 150 ns 150 ns 300 ns 125 ns
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SYMBOL tSToD tSTiS tSTiH
CHARACTERISTICS STIO1 Delay Level 2 Output STIO2 Set Up Time STIO2 Hold Time
MIN. 20 ns 30 ns 2 ns
MAX 125 ns
30ns
All specifications are for 2.048 Mb/s Streams and fCLK = 12.288 MHz.
6.4
EEPROM access
Timing diagram 2: EEPROM access
SYMBOL fSCL tSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU tDH
*)
CHARACTERISTICS Serial Clock Frequency Serial Clock Period Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Output Data Change after Clock Data In Setup Time Data In Hold Time
TYP. 32.2 KHz *) 1 / fSCL
3/4 tSCL 1/2 tSCL 1/2 tSCL 3/4 tSCL
10 ns 100 ns 100 ns
with 33 MHz PCI clock
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7
S/T interface circuitry
In order to comply to the physical requirements of ITU-T recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the HFC-S PCI needs some additional circuitry, which are shown in the following figures.
7.1
External receiver circuitry
VDD R1 C3 R2 R7 R3
LEV_R1
R1 R5 D1 R1 R5 LEV_R2 GND D3 D4 D2 VDD R6 12 14 RX R6 10 11 S/T module 5 RX + 16 S/T side
R2 R2 C3
R4 ADJ_LEV C1 GND
Figure 9: External receiver circuitry
Part list VDD R1, R1' R2, R2' R3 R4 R5, R5' R6, R6' R7 5V 33 k: 100 k: 1 M: 680k: 3.9 k: 4.7 k: 4.7 k: 1.8 M: 1.2M: 3.3V C1 C3, C3' D1, D2 D3, D4 S/T module 47 nF 22pF 1N4148 or LL4148 1N4148 or LL4148 see Table 3 on page 52.
C3, C3' are for reduction of high frequency input noise and should be located as close as possible to the HFC-S PCI.
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7.2
External transmitter circuitry
VDD R6 C3
R4
R5 T3 TX_EN
TX1_HI R1
TX2_HI
R1
T1
R7
T1
R2 T2 TX2_LO R3 T2 R3
R2
R8
TX1_LO GND
9 D2 GND D4 D5 7 ZD1 D3 8
S/T module
1 3 18
TX +
S/T side
TX -
Figure 10: External transmitter circuitry Part List VDD R1 R2 R3, R3' *) R4 R5 R6 R7 R8
*)
5V 2.2 k: 1% 3.0 k: 1% 18 : 100 : 5.6 k: 3.3 k: 3.3 k: 2.2 k:
3.3V 560 : 1% 3.9 k: 1% 18 :
0 :
C3 D2, D3 D4, D5 ZD1 T1, T1' T2, T2' T3 S/T module
3.3 k: 2.2 k: 1.8 k: 2.2 k:
470 pF 1N4148 or LL4148 1N4148 or LL4148 Z-Diode 2.7 V (e. g. BZV 55C 2V7) BC550C, BC850C or similar BC550C, BC850C or similar BC560C, BC860C or similar see Table 3 on page 52.
value is depending on the used S/T module
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S/T module part number APC 56624 APC 42624
manufacturer Advanced Power Components United Kingdom Phone: +44 1634-290588 +44 1634-290591 APC 5568DS (includes receiver and transmitter Fax: http://www.apcisdn.com circuitry) FE 8131-55Z FEE GmbH Singapore Phone: +65 741-5277 Fax: +65 741-3013 Bangkok Phone: +662 718-0726-30 Fax: +662 718-0712 Germany Phone: +49 6106-82980 Fax: +49 6106-829898 transformers: Pulse Engineering, Inc. United States PE-64995 Phone: +1-619-674-8100 PE-64999 Fax: +1-619-674-8262 PE-65795 http://www.pulseeng.com PE-65799 PE-68995 PE-68999 T5006 T5007 S0-modules: T5012 T5034 T5038 T 6040... VAC GmbH Germany transformers: Phone: +49 6181/ 38-0 3-L4021-X066 Fax: +49 6181/ 38-2645 3-L4025-X095 http://www.vacuumschmelze.de 3-L5024-X028 3-L4096-X005 3-L5032-X040 S0-modules: 7-L5051-X014 7-M5051-X032 7-L5052-X102 7-M5052-X110 7-M5052-X114 transformers: Valor Electronics, Inc. Asia ST5069 Phone: +852 2333-0127 S0-modules: Fax: +852 2363-6206 PT5135 North America ST5201 Phone: +1 800 31VALOR ST5202 Fax: +1 619 537-2525 Europe Phone: +44 1727-824-875 Fax: +44 1727-824-898 http://www.valorinc.com
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S/T module part number 543 76 009 00
transformers UT21023 S0-modules: UT 21624 UT 28624
manufacturer Vogt electronic AG Germany Phone: +49 8591/ 17-0 Fax: +49 8591/ 17-240 http://www.vogt-electronic.com UMEC GmbH Germany Phone: +49 7131-7617-0 Fax: +49 7131-7617-20 Taiwan Phone: +886-4-3590096 Fax: +886-4-3590129 United States Phone: +1-310-326-7072 Fax: +1-310-326-7058 http://www.umec.de
Table 3: S/T module part numbers and manufacturer
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7.3
Oscillator circuitry
Part list:
OSC_IN C1
Q1 R1 R2 C1, C2
12.288 MHz quartz 0..50 : 1 M: 47 pF
Q1
R2
OSC_OUT C2 R1
Figure 11: Oscillator Circuitry
The values of C1, C2 and R1 depend on the used quartz. For a load-free check of the oscillator frequency the C4O clock of the GCI/IOM2 bus should be measured (HFC-S PCI as master, S/T interface deactivated, 4.096 MHz frequency intented on the C4IO).
7.4
EEPROM circuitry
Figure 12: EEPROM circuitry
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7.5
PME pin circuitry
The PME pin (pin 53) on the HFC-S PCI is high active. To connect it to the low active PME# pin on the PCI bus, the following circuitry is neccessary.
Figure 13: PME pin circuitry
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8
8.1
State matrices for NT and TE
S/T interface activation/deactivation layer 1 for finite state matrix for NT
State name State number INFO sent
Reset G0
Deactive G1
Pending activation G2
Active G3
Pending deactivation G4
Event
INFO 0
INFO 0
INFO 2
INFO 4
INFO 0
State machine release (Note 3)
G2
|
|
|
|
Activate request
G2 (Note 1)
G2 (Note 1) |
| Start timer T2 G4
| Start timer T2 G4
G2 (Note 1) |
Deactivate request Expiry T2 (Note 2) Receiving INFO 0
] ] ] ] ] ]
] ]
G2 (Note 1) /
] ] ]
G3 (Note 1) /
]
G2
G1
G1
Receiving INFO 1
/
] ] ]
Receiving INFO 3
]
G2
Lost framing
/
Table 4: Activation/deactivation layer 1 for finite state matrix for NT
/ |
No state change Impossible by the definition of peer-to-peer physical layer procedures or system internal reasons Impossible by the definition of the physical layer service
Note 1: Timer 1 (T1) is not implemented in the HFC-S PCI and must be implemented in software. Note 2: Timer 2 (T2) prevents unintentional reactivation. Its value is 32ms (256 x 125s). This implies that a TE has to recognize INFO 0 and to react on it within this time. Note 3: After reset the state machine is fixed to G0.
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8.2
Activation/deactivation layer 1 for finite state matrix for TE
State name State number Info sent
Reset F0 INFO 0 F2
Sensing F2 INFO 0 / | | / F3
Deactivated F3 INFO 0 / F5 F4
Awaiting signal F4 INFO 1 / | | F3
Identifying input F5 INFO 0 / | |
Synchronized F6 INFO 3 /
Activated F7 INFO 3 / | |
Lost framing F8 INFO 0 /
Event
State machine release (Note 1) Activate Receiving any signal Request Receiving INFO 0 Expiry T3 (Note 5) Receiving INFO 0 Receiving any signal (Note 2) Receiving INFO 2 (Note 3) Receiving INFO 4 (Note 3) Lost framing (Note 4)
] ] ] ] ] ] ] ]
]
/
] ] ]
F6 F7 /
] ]
F3 F3 /
]
F5 F6 F7 /
] ]
F6 F7 /
F3
]
F3 / F6
] ] ]
F3
F6 F7
]
F7 F8
]
F7
F6
]
F8
]
Table 5: Activation/deactivation layer 1 for finite state matrix for TE
| /
No change, no action Impossible by the definition of the layer 1 service Impossible situation
Notes Note 1: After reset the state machine is fixed to F0. Note 2: This event reflects the case where a signal is received and the TE has not (yet) determined wether it is INFO 2 or INFO 4. Note 3: Bit- and frame-synchronisation achieved. Note 4: Loss of Bit- or frame-synchronisation. Note 5: Timer 3 (T3) is not implemented in the HFC-S PCI and must be implemented in software.
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9
9.1
Binary organisation of the frames
S/T frame structure
The frame structures are different for each direction of transmission. Both structures are illustrated in Figure 14.
Figure 14: Frame structure at reference point S and T
F L D E FA M
Framing bit D.C. balancing bit D-channel bit D-echo-channel bit Auxiliary framing bit Multiframing bit
N B1 B2 A S
Bit set to a binary value N = F A (NT to TE) Bit within B-channel 1 Bit within B-channel 2 Bit used for activation S-channel bit
* note! Lines demarcate those parts of the frame that are independently d.c.-balanced. The FA bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q bit transmission is enabled (see SCTRL register). The nominal 2-bit offset is as seen from the TE. The offset can be adjusted with the CLKDEL register in TE mode. The corresponding offset at the NT may be greater due to delay in the interface cable and varies by configuration. HDLC-B-channel data start with the LSB, PCM-B-channel data start with the MSB.
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9.2
GCI frame structure
The binary organistation of a single GCI channel frame is described below.
Figure 15: Single channel GCI format
B1 B2 M D C/I MR MX
B-channel 1 data B-channel 2 data Monitor channel data D-channel data Command/indication bits for controlling activation/deactivation and for additional control functions Handshake bit for monitor channel Handshake bit for monitor channel
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10 Clock synchronisation
10.1 Clock synchronisation in NT-mode
Figure 16: Clock synchronisation in NT-mode
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10.2
Clock synchronisation in TE-mode
Figure 17: Clock synchronisation in TE-mode
The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus twice for one half clock cycle. This can be reduced to one adjustment of a half clock cycle. This is useful if another HFC-S, HFC-S+, HFCSP or HFC-S PCI is connected as slave in NT mode to the GCI/IOM2 bus.
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11 HFC-S PCI package dimensions
Figure 18: HFC-S PCI package dimensions
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12 ISDN PCI card sample circuitry with HFC-S PCI
The 8-Bit-Flip-Flop (U3) is only needed for auxiliary port accesses. The EEPROM (U2) is also optional.
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Part List Part C1 C2 C3 C4 C7 C8 CB1 CB2 CB3 CB5 CB6 CB7 CB8 CB9 CON1 CON5 D1 D2 D5 D10 Value 47p 47p 22p 22p 47n 470p 33n 33n 33n 33n 33n 33u 10V, BF C 33u 10V, BF C 33n PCI32PME WESTERN BAV99 BAV99 Z-Diode 2V7 BAV99 Part D11 JP1 JP2 Q1 Q2 Q3 Q4 Q5 Q6 Q7 R1 R2 R3 R4 R5 R5' R6 R6' R7 R7' R8 R8' R9 Value BAV99 IOM PINHD-2X13 12.288 MHz BC850C BC850C BC850C BC850C BC860C BC850C (330R) (1M) 3k9 1M 4k7 4k7 4k7 4k7 100k 100k 33k 33k 1M8 Part R10 R11 R12 R13 R13' R14 R15 R15' R16 R16' R17 R18 R19 R20 R21 R22 R23 R24 TR1 U1 U2 U3 Value 100R 3k3 5k6 2k2 1% 2k2 1% 3k3 3k 1% 3k 1% 18R 18R 3k3 10k 10k none none 10k none none SOTR HFC-S PCI 24C04 74374 (optional)
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